The present invention covers a conversion unit forming part of a microprocessor that is an improved version of the Intel80386 microprocessor, frequently referred to as the 386 processor. In many applications, the 386 processor provides floating point data for the 80387 math co-processor, also frequently referred to as the 387 co-processor. The 387 processor includes a floating point execution unit which handles floating point arithmetic operations. Details of the floating point execution unit of the 387 are described in numerous publications (Intel 80386, 386, 80387, and 387 are trademarks of Intel Corporation).
It is well-known in the art that floating point data can have many different representations. Commonly, a user conforming to IEEE standard formats will provide data to a microprocessor in single precision real, double precision real, or extended precision real formats. Because of the difficulty in performing mixed format arithmetic operations (e.g., multiplication of a single precision real number by a double precision real number), many microprocessors convert floating point data to a predetermined standard format before beginning any operation. For instance, the 387 co-processor performs its floating point operations using a special internal format (the significance of the internal format will be explained in detail later). Therefore, it is necessary to convert all floating point data to the internal format of the 387 before performing any operations. After all arithmetic operations have been completed, the result can be converted back to any desired format of the user.
Although various circuits and schemes exist for converting floating point data formats within a microprocessor, they are typically time consuming, and therefore costly in terms of overall system performance. In the 387 co-processor, for example, the conversion step uses a finite state machine called a nanosequencer and requires two full clock pulses to complete.
Because floating point data operations are themselves very time consuming and, for scientific applications, comprise about 25-30% of all opertions within a microprocessor, it is desirable to have circuitry that could convert the data to the required format much faster. Thus, what is needed is a new approach that detects when floating point data is about to be loaded and then converts that data to the required format prior to the storage of the data in a register.
FIG. 2 illustrates the difference between the conversion process of the 387 co-processor (representing the prior art) and the present invention. In the prior art, floating point data initially resides in a FIFO (first-in-first-out) memory unit which corresponds to the cache memory in the present invention. When a microcode instruction calling for the loading of a floating point number is received by the floating point execution unit (commonly referred to as the "Funit"), the number is latched into the Funit interface latch in response to CLK1. The exponent portion of that number is then separated from its mantissa and stored in an exponent register. This occurs at CLK2. Afterwards, a convert operation, which requires two clock pulses to complete, is initiated. The conversion is performed using a nanosequencer. Upon the transmission of CLK4, the converted exponent is transferred back to the exponent register. Finally, clock pulse CLK5 sends the converted exponent to the floating point stack (FP Stack) where it is available for arithmetic operations (i.e., addition, subtraction, multiplication, etc.).
In contrast, the present invention is capable of performing a format conversion as the number is being loaded from the Funit interface latch to the exponent register. Consequently the converted floating point number is presented to the FP stack at CLK3 instead of at CLK5 as shown in the flowchart of FIG. 2. By eliminating the two clock pulses normally required for the convert operation, a 40% increase in floating point processing speed is realized. Such an increase is significant in the overall performance of a microprocessor system.
As will be seen, the present invention permits conversion to be performed as described above, i.e., "on the fly". This capability enhances the presently described microprocessor when compared to prior art processors.